The present invention relates to the mounting of integrated-circuit chips on a ceramic or other carrier substrate, and more specifically concerns the physical layout of conductors on the substrate for connecting the chips to each other and to other components.
One conventional technique for connecting integrated-circuit (IC) chips to each other and to other components is to mount them on a ceramic substrate having a pattern of conductors deposited on its surface. These conductors are substantially linear, and terminate in an array of small round pads under the chip. The chip carries a mating array of small projections called solder bumps or C4 (controlled-collapse chip connection) contacts. The chip is bonded to the substrate by applying a flux to the pads, aligning the C4 contacts over the mating pads, and applying sufficient heat to reflow the solder onto the pads, thus forming both a mechanical bond and an electrical contact between each pad and its mating contact.
One of the major barriers to increasing the amount of function which can be integrated in microelectronics technology is the number of off-chip connections which can be brought into a single chip. The ultimate restriction is the maximum escape number for a given minimum conductor pitch and chip size. If a circle is drawn around a neutral point at or near the center of the chip, the length of its circumference divided by the pitch or distance between adjacent conductors gives an approximate value for the maximum escape number. The radius of this circle ("distance from neutral point" or DNP) can be as large as the chip itself, although there are reasons for keeping the DNP smaller. For example, differential thermal expansion between the chip and the substrate stresses the contacts in proportion to the DNP; this is a major factor in the reliability of microelectronic circuits. The actual escape number is limited to less than its maximum value by another factor. The pads terminating each conductor are larger in width than the conductors, and therefore require a larger pitch or spacing, usually about three to four times the conductor pitch. If the pads are merely arranged in a circle at the DNP, the actual escape number is limited by the larger pad pitch. To improve this situation, the pads must use more of the area under the chip, within the DNP circle.
The prior art has developed many wiring patterns for mounting an integrated-circuit chip on a substrate with C4 contacts. The simplest configuration or footprint is a completely filled square or rectangular array of solder bumps and mating circular pads on the substrate. The problem here, however, is that the conductors must snake between the pads to escape from under the chip. This decreases the realizable pad pitch by appropriating some of it for the conductors. The most common expedient is a partially depopulated array. For example, a number of pads in a central region of the chip can be omitted; in the extreme case, this would leave only a single line of pads in a square near the chip edges and inscribed in the DNP circle. Some of the pads can alternatively be omitted on the periphery of the array, giving it a puckered or scalloped shape.
All of the prior approaches fall short of attaining the maximum escape number for a given maximum DNP. Moreover, many prior attempts are of an ad-hoc nature, without any overall strategy which could be employed to guide the design of wiring configurations for a large number of different chips. The major single drawback of conventional wiring patterns for the pads and conductors is that they require conductors to pass between pads. As previously stated, such patterns always decrease the pitch of the pads, forcing them to occupy a larger overall area than necessary. In addition, they generally force the conductors into contorted paths through the thicket of pads; this greatly increases the design effort and also degrades the current-carrying capability of the conductors by increasing their length to the DNP circle or boundary.